System-on-Chip & System-in-Package Design
Our SoC-SiP Design service offers our customers a single point of contact for SoC-SiP integration starting from high-level marketing specifications down to tape-out to a foundry. Essensium handles the whole design chain and adds key value to the stages of the development with the highest impact on the successful delivery of a competitive SoC solution:
- Architecture design
- IP integration
- Top level verification
- SW integration
Essensium maximizes the benefits of any SoC-SiP implementation by optimizing the SoC-SiP architecture through the correct trade-offs between different technologies , analog and digital, and hardware and software. At the same time, Essensium builds a framework to validate the individual components and to guarantee the correct interoperability and overall performance and quality of the SoC-SiP.
We offer a full end-to-end design flow starting from marketing requirements or a partial flow, depending on the customers desired involvement in the SoC-SiP design.
Our SoC-SiP development services starts from the customer's high level marketing specification and takes it down to a fully qualified SoC-SiP product. Essensium handles all intermediate stages of the design, comprising:
- Design of the SoC-SiP architecture, resulting in a set of technical specifications, hierarchically from top-level to individual modules; it involves exploration of architecture alternatives, including multi-chip, analog/digital, hardware/software and cost/performance trade-offs, as well as the availability of standard dies in different technologies and IP.
- Creation of a system-level model capable of co-simulating both analog and digital hardware descriptions as well as software. This model is the core of our design flow and serves the dual role of executable specification and verification framework.
- Detailed module design and functional verification, typically relying on internal and/or partner's IP blocks. Depending on the application, this may also include the development of embedded and/or application software .
- ASIC back-end including layout, timing closure, DRC and final functional verification with a back-annotated net list. We are particularly specialized in resolving the co-existence issues between sensitive analog macros with digital circuitry.
When the silicon is available and tested for functionality and performance, Essensium can perform HW bring-up and SW integration services to enable SW application developers easy access to the hardware.
Our complete SoC-SiP design flow covers system, front end, and back end design.
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- Convert marketing requirements into high-level technical specification.
- High-level cost, power consumption, and performance evaluation
Definition and Pre-Study
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- Detailed functional specification
- Algorithm development
- modulation, channel coding, source coding, audio/video processing
- Architecture definition
- HW/SW partitioning
- Analog/digital trade-off analysis and partitioning
- Memory selection
- Detailed technical specification of sub-systems
- Proposal for IP to be sourced or to be developed.
- High level system-C modeling
- Detailed design project schedule
System Design
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- RTL code generation
- RTL verification
- RTL synthesis
- Analog-mixed signal macro design
- ATPG, Power optimization, boundary scan, BIST
- Post synthesis simulation
Front End Design
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- Floor planning and I/O placement
- Timing analysis
- Unit delay gate level simulations
- Top IP/IC level routing
- IP/IC GDSII generation
- DRC, ERC, LVS checking
- RC parasitic extraction
- Post lay-out timing, power and cross talk analysis
- Timing closure
- Final GDSII Database
Back End Design
